1. Field of the Invention
The present invention related in general to bit line sense amplifier circuits and more particularly to a bit line sense amplifier circuit in which a voltage controllable driver is used in generating a restore signal or a sensing signal, the voltage controllable driver performing a voltage switching operation in response to a control signal to reduce the noise component in power supply lines.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a circuit diagram of a conventional bit line sense amplifier circuit. As shown in this drawing, the conventional bit lie sense amplifier circuit comprises a bit line sense amplifier 11 for sensing data on a bit line, a precharge circuit 12 for precharging P-channel and N-channel cross coupled latch enable signals rtoi and sbi, a restore signal circuit 13, and a sensing signal circuit 14.
The operation of the conventional bit line sense amplifier circuit with the above-mentioned construction will hereinafter be described with reference to an operating timing diagram of FIG. 2.
The bit line sense amplifier 11 includes a P-channel cross coupled latch an N-channel cross coupled latch, a bit line precharge circuit, a memory cell and a column select circuit.
In the bit line sense amplifier 11, the bit line is precharged with a voltage level Vblp (about Vcc/2) at a precharge state. Namely, at the precharge state, a control signal blp2 becomes high in logic under the condition that a signal /RAS is high in logic. As a result, NMOS transistor Q5-Q7 are turned on to precharge the bit line with the voltage level Vblp (about Vcc/2).
At an active state, the control signal blp2 goes from high to low in logic under the condition that the signal /RAS is low in logic. As a result, the bit line becomes floated.
On the other hand, if a word line wl is enabled, an NMOS transistor Q10 is turned on to transfer a voltage stored on a capacitor cs to the bit line. As a result, a voltage .DELTA.V is added to an initial voltage or Vcc/2 on the bit line.
The column select circuit is used for the data transfer between bit lines BL and /BL and data bus lines db and /db when a control singal yi is high in logic.
The precharge circuit 12 includes three NMOS transistors Q11-Q13. The NMOS transistor Q11 has a gate terminal for inputting a control signal blp1, a drain terminal for inputting the voltage Vblp and a source terminal connected to a node N3. The NMOS transistor Q12 has a gate terminal for inputting the control signal blp1, a drain terminal for inputting the voltage Vblp and a source terminal connected to a node N4. The NMOS transistor Q13 has a gate terminal for inputting the control signal blp1, a drain terminal connected to the node N3 and a source terminal connected to the node N4.
In the precharge circuit 12, the P-channel and N-channel cross coupled latch enable signals rtoi and sbi are precharged with the voltage level Vblp at the precharge state. Namely, at the precharge state, the control signal blp1 becomes high in logic under the condition that the signal /RAS is high in logic. As a result, the NMOS transistors Q11-Q13 are turned on to precharge the P-channel and N-channel cross coupled latch enable signals rtoi and sbi with the voltage level Vblp.
At the active state, the control signal blp1 goes from high to low in logic under the condition that the signal /RAS is low in logic. As a result, the P-channel and N-channel cross coupled latch enable signals rtoi and sbi become floated so that the restore and sensing signal circuits 13 and 14 can be operated respectively in response to clock signals /R1 and S1 being enabled after a predetermined time delay from the control signal blp1.
The restore signal circuit 13 includes a PMOS transistor Q14. The PMOS transistor Q14 has a gate terminal for inputting the clock signal /R1, a drain terminal connected to a supply voltage source Vcc and a source terminal connected to the node N3.
When the clock signal /R1 goes from high to low in logic, the PMOS transistor Q14 is turned on to transfer a supply voltage from the supply voltage source Vcc to the node N3. As a result, the P-channel cross coupled latch is operated in response to the supply voltage on the node N3. The P-channel cross coupled latch is provided with two PMOS transistors Q1 and Q2.
The sensing signal circuit 14 includes an NMOS transistor Q15. The NMOS transistor Q15 has a great terminal for inputting the clock signal S1, a drain terminal connected to the node N4 and a source terminal connected to a ground voltage source Vss.
When the clock signal S1 goes from low to high in logic, the NMOS transistor Q15 is turned on to transfer a ground voltage from the ground voltage source Vss to the node N4. As a result, the N-channel cross coupled latch is operated in response to the ground voltage on the node N4. The N-channel cross coupled latch is provided with two NMOS transistors Q3 and Q4.
In the above-mentioned conventional bit line sense amplifier, the P-channel and N-channel cross coupled latch enable signals rtoi and sbi may be coupled to a plurality of sense amplifiers, i.e., 1K or more. For this reason, when the P-channel and N-channel cross coupled latch enable signals rtoi and sbi are operated as restore and sensing signals in response to the enable clocks /R1 and S1, respectively, abrupt current flow di/dt may occur in the PMOS transistor Q14 and the NMOS transistor Q15, resulting in the generation of a noise component in the power supply lines Vcc and Vss. Further, the noise component is significantly increased according to a variation of the supply voltage, resulting in a faulty operation of the circuit.